1. Field of the Invention
This invention relates to a semiconductor device manufacturing method, particularly, a method of manufacturing a chip size package type semiconductor device.
2. Description of the Related Art
CSP (Chip Size Package) has received attention in recent years as a packaging technology. The CSP means a small package having almost the same outside dimensions as those of a semiconductor die packaged in it. Conventionally, BGA (ball grip array) type semiconductor devices have been known as a kind of CSP type semiconductor devices. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on one surface of the package, and electrically connected with the semiconductor die mounted on the other side of the package.
When this BGA type semiconductor device is mounted on electronic equipment, the semiconductor die is electrically connected with an external circuit on a printed circuit board by compression bonding of the ball-shaped conductive terminals to wiring patterns on the printed circuit board.
Such a conventional BGA type semiconductor device is manufactured by a following manufacturing method, for example.
First, a semiconductor substrate sectioned by a dicing line is prepared. Electronic devices are formed on a front surface of the semiconductor substrate. Then, pad electrodes connected with the electronic devices are formed on the front surface of the semiconductor substrate. Furthermore, a support body is formed on the front surface of the semiconductor substrate. Then, openings exposing the pad electrodes are formed along the dicing line by selectively etching a part of the semiconductor substrate from its back surface. A wiring layer is then formed, being electrically connected with the pad electrodes exposed in the openings and extending from an inside of the openings onto the back surface of the semiconductor substrate. Furthermore, the wiring layer is selectively etched to form a predetermined wiring pattern. Then, a protection layer exposing a part of the wiring layer is formed on the back surface of the semiconductor substrate including on the wiring layer, and conductive terminals are formed on a part of the wiring layer. Finally, the semiconductor substrate is separated into a plurality of semiconductor dice by dicing along the dicing line. The relevant technology is disclosed in the Japanese Patent Application Publication No. 2002-512436.
By the conventional BGA type semiconductor device manufacturing method described above, the wiring layer formed on the back surface of the semiconductor substrate is separated along the dicing line DL together with the semiconductor substrate when dicing is performed. Alternatively, the wiring layer is separated by patterning after the wiring layer is formed. Next, the process of separating the wiring layer formed on the back surface of the semiconductor substrate will be described with reference to drawings. FIGS. 19 to 21 are cross-sectional views showing the conventional semiconductor device manufacturing method. FIGS. 19 to 21 show a portion near the dicing line DL of the semiconductor substrate formed with an opening.
As shown in FIG. 19, when a wiring layer 58 on a back surface of a semiconductor substrate 50 including an opening 50w is separated by dicing, a dicing blade 40 comes in contact with the wiring layer 58 and makes stresses or impact on it. This causes damages to the wiring layer 58 such as peeling. Furthermore, although not shown, moisture used for dicing or cutting dust remains on a cut surface of the wiring layer 58, causing corrosion in the wiring layer 58 after dicing. That is, reliability of the semiconductor device reduces.
In a case that the wiring layer 58 is separated by patterning after the wiring layer 58 is formed on the back surface of the semiconductor substrate 50 including the opening 50w, as shown in FIG. 20, the described dicing blade need not be used. In this method, a resist layer 59 (made of a negative resist layer) as an etching mask is formed on the wiring layer 58, and the wiring layer 58 is selectively removed by etching.
However, when exposure is performed, using a mask 60 for patterning the resist layer 59, light reflected at the resist layer 59 formed on a sidewall of the opening 50w reaches the resist layer 59 at a bottom of the opening 50w under the mask 60. Therefore, as shown in FIG. 21, the resist layer 59a to be removed is failed to be removed and remains. Although not shown, when etching is performed using the resist layer 59 as an etching mask after then, too, the wiring layer 58 to be removed is failed to be removed and remains. In this case, the wiring layer 58 remains on the dicing line DL to become an obstacle to dicing, so that reliability of the semiconductor device reduces like in the described method of separating the wiring layer 58 by dicing.